Parallel wideband digital up‐conversion architecture with efficiency
نویسندگان
چکیده
منابع مشابه
An Efficient Parallel Architecture for Wideband Digital Down Conversion ⋆
Intermediate frequency (IF) processing bandwidth has long been a bottleneck, because of the restriction caused by the processing speed of digital signal processing devices. Field programmable gate array (FPGA) can not provide the data processing speed that matches the sampling rate to perform direct wideband digital down conversion. That’s why a parallel architecture, which involves parallel de...
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ژورنال
عنوان ژورنال: The Journal of Engineering
سال: 2019
ISSN: 2051-3305,2051-3305
DOI: 10.1049/joe.2018.9061